[Coco] hardware question - coco3 RAM subsystem

[jdaggett at gate.net]

Stephan

First off the COCO3 DRAM is configured in 256Kx16 mode using 41256 
drams.  DRAM access is fixed time and is accessed via a method known as 
IDMA(Interleaved DMA). That is when the E Clock is low the GIME 
accesses the memory for video. During the protion when the E Clock is 
high the CPU will write to memory. All reads of memory pass through the 
GIME chip. 

If your SRAM can be used in either 8 or 16 bit data buss mode then with 
fast enough external glue logic it maybe possible to be used in a COCO3. 

james

On 26 Mar 2009 at 11:13, Stephen Adolph wrote:


> Hi folks,

> new to list, nice to meet you all.

> 

> Ok, here is my question.  Looking at the 512k upgrades for Coco3, I

> understand this is a DRAM based system.

> 

> I happen to have a large amount of 2MB SRAMs, and a custom board with

> a CPLD, that could be used to do a variety of things.

> 

> (actually it is a ReMem for the M100 - see www.istop.com/~sadolph -

> that's me.) (I want to reuse some existing memory hardware to upgrade

> the COCO3 I have).

> 

> 

> So, I am looking at the 41256 data sheet, and thinking about using

> SRAM instead of DRAM.

> 

> But, 41256 has some memory modes "page mode" that allows the row to

> remain while the column is stobed..to up the read/write rate I

> presume.

> 

> Does COCO3 use these modes? OR, does it always operate in such a way

> that CPU bus memory address always translates to one and only one

> memory read/write?

> 

> OR, could I simply capture ROW and COLUMN and create my own address

> from that.

> 

> ( I don't know enough about how the GIME chip manages the ram is what

> this boils down to.)

> 

> pls advise if possible.

> 

> cheers,

> Steve

> 

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