[Coco] 6551 at 115200 bps (Roger's CoCo Net)
operator at coco3.com
Sun Jan 18 19:43:01 EST 2009
At 05:49 PM 1/18/2009, you wrote:
>>To Roger and all...
>>On a side note: This need for quick timing loop is why Tandy used
>>the Halt and Load design for the Floppy Disk Controller. The
>>timing was too tight to have the CPU test for a byte being ready so
>>they just halted the CPU till till the byte was there. (It was up
>>to the interrupt to end the reading loop.) Not the best
>>design. But it was cheap and worked.
>It is doable, but it does require some 6809 tricks to do it, the
>Dragon Floppy controler did it by setting DP to $FF so that it could
>address the WD2797 with a 1 byte address as opposed to 2, e.g. LDA
>$40 instead of LDA $FF40 etc which saved a read cycle, and then used
>an FIRQ/SYNC loop to process the data, with NMI to break out of the
>loop when done.
Most stuff is doable given enough thought. Maybe the 6551 IRQ
triggering the CoCo's FIRQ routine could save the current PCR, save
the current Data In byte, jump back into the mainline code at a Read
Buffer routine that disables FIRQ temporarily, reads a chunk of data
manually using very tight code and by checking the 6551 status bits
until no data is there, enabling FIRQ and returning to PCR where FIRQ
first interrupted. The fact that no data is present when the manual
reader stops might mean there is time for another FIRQ to happen
again without missing data. Things like this would have to be tested
extensively using all sorts of high level protocols like XMODEM-CRC,
Y-MODEM, etc. to see how things behave at 115200 bps. A long
continuous stream of incoming data could be a problem, but who
knows. This is why the RTS/CTS signals should be utilized.
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