[Coco] hard disk performance

[Gene Heskett]

On Friday 26 September 2008, Chuck Youse wrote:
>So, quick question, folks - does anyone have any basic performance data
>for hard disks on 6809 NitrOS-9 Level II systems?  I only ask out of
>curiosity; I've tweaked my HDISK driver to get probably fairly close to
>maximum performance out of it (without being rude to the rest of the
>system by disabling interrupts or doing any busy-waiting) and megaread
>reports about 45K/sec transfers.  As far as usability goes, it seems
>pretty peppy - and given that it's written to be nice to a multi-tasking
>system, heavy disk I/O doesn't impact the rest of the system much
>(interactive processes remain beautifully responsive).

You are getting about 22 seconds for a megabyte then, which is about half 
speed.  I'm doing it from a scsi hard drive in 11 seconds, or from "myram" in 
that same 11 seconds.  That is using block moves in myram, which is as fast 
as the 6x09 can move data.

>I vaguely recall seeing numbers from megaread in the 70-80K range
>(reported by others), and I'm wondering how much of this is just a
>limitation of my hardware design, how much is due to the fact that I'm
>running on a stock 6809 Coco 3 vs a 6309-enhanced one.

The stocker should be able to do that in 15-17 seconds.  I think... Myram when 
built for the 6309, is using the ldq/stq in a loop, 4 bytes moved per pass 
through the loop.  The 6809 can only move 2.  But in any event the buss is 8 
bits wide, so either is actually doing 8 bit reads and writes on a given 
machine cycle.

>Any info out there?
>
>I have to say; back when I was a poor kid with a 128K Coco 3 and a pair
>of single-sided drives and a black/white TV, I loved the OS-9.  The
>addition of a hard disk makes the system a thousand times more useful.
>What a beautiful thing.

Amen.

>C.
>
>[For those who are curious, some of the 'limitations of the design' I
>refer to above include not being interrupt-driven and having to diddle
>with MPI.Slct to map the hardware registers into FF40-FF4F, which
>necessitates quite a few cycles to read/write a register.  During the
>PIO transfers I try to group the transfers into 8s to minimize the
>overhead and simultaneously allow timely servicing of system
>interrupts.]
>
>
>
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-- 
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