[Coco] CoCo 1 64K upgrade failed :(.

[Chuck Youse]

On Fri, 2008-09-26 at 16:05 -0500, Ryan Pritchard wrote:
> I don't understand why the SAM is only refreshing at 128 cycles.  You have 8
> address bits getting latched on RAS and then the next 8 bit being latched on
> CAS.   Wouldn't 8 address bits mean 256 cycles?  Or is the refresh occuring
> for 2 rows per cycle?

Well, that's ordinarily what happens during an access cycle - and a side
effect of the access cycle is a refresh of the column in question (I
always get them confused.. but it's EITHER the column or the row, I just
forget - let's call it columns for now).

But - in order to maintain the contents of all the columns, you must
access every column once every, oh, say, 2ms.  (The actual time depends
upon the chips in question.)  In software this is sometimes possible via
an interrupt or somesuch (and early PCs did this with an extra channel
on the DMA controller) but on the Coco it's done with the SAM, which
interleaves these accessing-every-row refresh cycles in between CPU
cycles (it also uses those times to grab video data for the VDG).

Ok, sorry, I'm getting windy.  The point is that the LS783 SAM only has
a 7-bit counter; so it'll refresh rows 0-127 and then start all over
again, never hitting the upper half.  For 64K DRAMs this is fine, as
they only require a 128-cycle refresh.  For the 256K DRAMs this can be
problematic.  As PHS pointed out the 74LS785 can be configured for a
full 256-cycle refresh (which, if you consider for a moment, also means
the refresh PERIOD is twice as long).

Blah blah blah.  Blah, blah blah blah blah!!  Blah. 

Hope this makes SOME sense.

C.