[Coco] CoCo 3 MMU test for all

[Mark Marlette]

Roger,

You must be still sleep deprived or you don't understand the GIME.

I always thought programmers did it in hex? I know hardware designers do!

Per your table below. You can't look at it that way. Bits 6/7 ARE NOT 
READABLE. That is why you AND out bits6/7.

128k: 112-127  s/b 0-$0f
512k: 64-127   s/b 0-$3f
1 meg: 64-255  s/b 0-$7f
2 meg: 0-255   s/b 0-$ff  (only one you got right, think hex, it is easier)

Use the source Luke! CC3 Technical manual.

There is no gathering, it is how I described. Not sure how P-3 ever 
worked based upon your table. You must have forgotten or wild things 
will happen with the P-3 on systems larger than 512k.

I still follow Tandy's design guidelines. The SB is going to violate 
a few of the rules but then Tandy isn't making the CoCo anymore. So I 
don't have anything to worry about. I know the internal workings of 
the CoCo, period. Spent many hours writing test code and watching how 
the machine responds. There is A LOT of info missing or very vague in 
the CC3 tech manual. Emulators are great but still don't beat the 
real thing. Hard to create/test when one doesn't own a real CoCo3.

Regards,

Mark


Reread my original post.
At 1/20/2008 07:06 PM, you wrote:


>At 03:49 PM 1/20/2008, you wrote:

>>Roger,

>>

>>I haven't been following this that close because it is something I 

>>do everyday.

>>

>>As james has indicated, basic CoCo understanding of the CoCo's 

>>internal registers. A stock MMU is only 6 bits wide. 'AND' off the 

>>upper two bits, bit6 & bit7.

>>

>>Go to a 1 meg machine and bit0-6 will be used.

>>

>>Go to a 2meg machine and bit0-7 will be used.

>>

>>256 blocks of 8k sized blocks = 2megs.

>>

>>Mark

>>Cloud-9

>

>At least one of my comments were "sleep deprived" 

>comments.  ;)  I've written programs like P-3 that take advantage of 

>the full 512k memory map in a tricky way but using apparent blocks 

>0-63.  If 64 is added by the GIME for 128-512k CoCo's then I suppose 

>it really means blocks 64-127 for 512k, and 112-127 for 128k even if 

>you poke 0-63, while 1 meg upgrades *may* set the highest bit 7 by 

>default to give the same behavior to push the blocks upward in the 

>same fashion?

>

>If so, what is now apparent for the actual hardware block #'s 

>(regardless of what a PEEK reveals at the prompt for an MMU register 

>for 128k-512k CoCo's):

>

>128k: 112-127

>512k: 64-127

>1 meg: 64-255

>2 meg: 0-255

>

>Somebody will correct me if I'm wrong, but this is what I'm 

>gathering.  For a stock CoCo 3, blocks are referenced as 48-63, though.

>

>

>

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