[Coco] 6309 instruction timing question

[Darren A]

On 8/27/08, William Astle <lost at l-w.ca> wrote:
>
> Upon reflection, that might be the reason the "branch" instructions do
> not execute 1 cycle faster in native mode. The cycle saved by the
> prefetch of the opcode is used to load the prefetch cache based on the
> result of the jump. Sort of a primitive pipeline stall. The CPU resolves
> the branch, loads the program counter, does the prefetch, then continues
> as normal.
>

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Good point.  It's interesting that the BRA instruction always uses the
same number of cycles, but LBRA uses one fewer in native mode.

By the way, if you are relying on the Chet Simpson document for your
timing reference, you should know that some of the information is
incorrect (mainly the indexing modes involving W).

Darren