[Coco] 6309 Weirdness ??

[jdaggett at gate.net]

On 17 May 2007 at 10:28, Darren A. wrote:

> Okay, I am giving up on this one. Obviously, using the PC register in
> any of the new inter-register instructions is, to say the least,
> problematic.  I think my documenation for these instructions will say
> something like:
> 
> "Specifying the PC register as either the source or destination
> produces undefined results."
> 
> I'm not quite sure what the solution should be for MESS emulation.
> 
> I agree with Robert that these probably should have been treated as
> illegal instructions and invoked the trap.  Of course, Hitachi never
> sanctioned the use of any new features, so its quite possible they
> didn't bother to bullet-proof everything.
> 
> Darren
**************

Darren 

That is probably why Hitachi never officially published information on these 
insructions and the enhancements. Instead they decided to market the chip as a 
CMOS alternative to the NMOS HD6809/MC6809 chip. 

CMOS is inherently lower poser consumption than NMOS and would be yield a 
better marketing tool over the Motorola and other second source NMOS parts. My 
guess is that Hitachi wanted to develop a chip that was software compatible and 
hardware superior to the Motorola original and the many second sourced vendors. 
Looking backnow is retrospect, the design was not bullet proof. Any corrections 
would require major silicon change and figure management decided not to invest 
anymore into the project. 

It does appear that most of the issues come when the MD register bit 0 is set. I 
personally don't like the standard description given to this bit as "emulated" and 
"native" modes. Instead from the discussions over the years I tend to believe that 
this bit was used to enable and disable a crude primitive instruction pipeline 
feature to speed up operation. Why I say this is because from my understanding 
the new instructions and registers are available irregardless of the state of bit0 in 
the MD register.  What I do like about bit1 of the MD register is the way the FIRQ 
is handled. When the FIRQ mimics the IRQ function this then becomes a two 
level priority interrupt handler. IRQ has higher priority than FIRQ. Increases the 
number of IRQs up to 16. 

just some observations and thoughts

james