[Coco] POKE 65495,0

[Darren A.]

>From: Diego Barizo <diegoba at adinet.com.uy>
>
>According to a text in
>http://www.old-computers.com/museum/computer.asp?st=1&c=508
>the double speed poke did not really switch the machine to 1.8 MHz.
>
>That doesn't seem right... or is it?
>
>Diego
>
-
Here is how the datasheet for the SAM describes the different MPU rate 
modes:

Two bits in the SAM control register determine the period of both "E" and 
"Q" MPU clocks. Three rate modes are implemented as follows:

SLOW: (0,0) The frequency of "E" and "Q" is 'crystal divided by 16'. This 
rate mode is automatically selected when the SAM is reset. The system timing 
is least critical in this "SLOW" rate mode.

A.D.  (0,1) The frequency of "E" and "Q" is either 'crystal divided by 16' 
or 'crystal divided by 8', depending on the address the MPU is presenting*.

FAST  (1,X) The frequency of "E" and "Q" is 'crystal divided by 8'. This is 
accomplished by stealing the time that is normally used for VDG/REFRESH, and 
using this time for the MPU. Neither VDG display nor dynamic RAM refresh are 
available in the "FAST" rate mode. Both are available in SLOW and A.D. 
modes.

*When the SAM control register bits "R1" and "R0" are programmed to "0" and 
"1" respectively, the Address Dependent Rate Mode is selected. In this mode, 
the 'crystal divided by 16' MPU rate is automatically used when addressing 
within $0000 to $7FFF, or $FF00 to $FF1F ranges. Otherwise the 'crystal 
divided by 8' MPU rate is used. This mode often nearly doubles the MPU 
throughput while still providing transparent VDG and dynamic RAM refresh 
functions. For example, since much of the MPU's time may be spent performing 
internal MPU functions, accesing ROM ($8000 to $FFEF) or accessing I/O 
($FF20 to $FF5F), the faster 'crystal divided by 8' MPU rate may be used 
much of the time.

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