[Coco] What about the double speed upgrade?

[Joel Ewy]

jdaggett at gate.net wrote:
> PCs have gone beyond just clock multiplying alone. AMD/Intel with their more 
> modern processors now have two busses. One to access ram and slower 
> peripheral and the other bus to communicate with the rest of the chipset,  ie 
> graphic controller.
>
> james
>   
> On 6 Jan 2007 at 0:17, Diego Barizo wrote:
>   
>> I might be wrong, but... Isn't that the same that PCs do?
>> A 400 MHz CPU and the bus at 100 MHz...
>> If so, does it have the same implications for any computer? 2 times
>> the CPU speed, same bus, just a 30% real speed increase?
>>
>> Diego
>>
>>     
Yeah, and they have all kinds of other things like 1 and 2 levels of
on-chip cache, pipelining, out-of-order instruction execution, branch
prediction, and now multiple CPU cores on the same chip.  But insofar as
it relates to increasing the CPU clock without increasing the bus clock,
Diego has the right idea.  But the "30% real speed increase" or
whatever, becomes much more when you have on-chip caches like the modern
microprocessors do.  Then much more of the processing can be done at the
higher rate, and slower external bus accesses are reduced.

<digression>Not that you're suggesting this, but the only way the CoCo
could have separate memory and I/O busses would be if the 6809 were
replaced by an FPGA board configured as a 6x09 with a built-in MMU and
memory controller on a separate bus from the rest of the computer.  Of
course, it would be possible (soon, if not with currently available
FPGAs) to stuff the entire CoCo into the chip, and add all kinds of
enhancements, like caches, extra CPU cores, extra CPU instructions and
addressing modes, an FPU, dynamically swappable special purpose
computing blocks, the fabled 256 color mode for the GIME, and more. 
(How about special hardware to provide explicit support for the flicker
display modes?)  Not to mention the fact that you could clock the CPU
much higher to begin with.</digression>

JCE
>> Richard E. Crislip wrote:
>>     
>>> On Thursday 04 January 2007 17:58, jdaggett at gate.net wrote:
>>>   
>>>       
>>>> SPeed compatibility issues will exist with either processor when
>>>> doing anything outside the processor. All the existing peripheral
>>>> devices would have to be of equal speed grade with the E clock.    
>>>>         
>>> <snip>
>>>
>>> That was the same problem the Amiga guys ran into when they tried to
>>> accelerate the Amiga beyond 7mhz. The supportring chips would not
>>> tolerate being sped up, so everything had to go around them and only
>>> bring them in at the correct moment.
>>>       
>> ...
>>