[Coco] COCO DTV

[ben jimenez]

Thanks for the info, I have a grocery list here!

jdaggett at gate.net wrote: Ben

Okay here is what I suggest.

1) I would go to Xilinx webpage, www.xilinx.com, register and download the free 
version of Webpack ISE. I beliewve they are at version 9.1 along with any service 
packs. 

2) Next go to Digilent Webpage, www.digilentinc.com and download three very 
large video tutorials. two are about 100megabytes. 

    introduction to VHDL is ~60 MB and is a starrter.
 Circuit Simulation is ~100MB
 BAsic Schematic and Simulation is ~100MB

3) subscribe to comp.lang.vhdl and comp.arch.fpga. There are some good people 
with a lot of knowledge there and you can pick up some tips there. 

4) I suggest finding a textbook and studying that. There are some books that are 
centered around learning VHDL and WEbpack ISE. Also if you are not familiar 
with computer logic then I would suggest a book on that. There are some good 
one and bad ones. The one I used in college was by Morris Mano and is a bit 
dated. His texts have een ridiculed by some students as difficult to learn. I found 
that I did have to read carefully and sometime reread. I found that after the 
pressures of multiple classes,  his work is not all that bad if you take it slowly. In 
fact the book I  have lays the framework of how a CISC microprocessor works. 

5) Get some literature on how to write testbenchs. This is HDL code that wraps 
around y our code to help simulate your code. In my knowledge, that is where I 
am the weakest and where some texts are also very weak.

Webpack ISE has with it a bunch of templates that help in learning how to code. 
Also ISE has a syntax ch ecker so that if you code something wrong it will tell 
you. VHDL is like a programing language. In my opinion it looks like a 
combination of Pascal and ADA. As Ben Cohen stated VHDL describes structure 
or it describes behavior. 

What you do with a HDL is describe the structure,gates and logic,  or you 
candescribe the behavior and then let the synthesis tool actually configure the 
FPGA into the actual gates. In reality a FPGA is not a bunch of AND,NAND, OR 
gates and such. A FPGA main building block is a 4 input LUT, Lookup Table. 
With one or more LUS you can configure them to act as any logic gate from 2 -
input and gates to 32 to one 8 bit wide multiplexers. 

VHDL and Verilog have now been used for about ten years or more in the design 
of not only FPGAs but in ASICs. What the languages do is to allow the designer 
to simulate the circuit before any commitmant to silicon. ASIC fabrication for just 
a few parts to verify design still can cost upwards to $200,000 for say 50 parts. If 
they are wrong then, that is wasted money and time. For example to fabricate a 
MC68HC11 microcomputer it takes upwards to 19 to 26 weeks. Before HDL 
language, IC fabrication and design process was a two to three year process to 
get a fully functional device ready for production. HDL language has cut that 
down now to a year to year and a half. 


Remember the early stages of learning will be overwhelming. In fact I am still 
learning nuances and interesting things. Learning to design ICs is and can be fun. 

james


On 15 Feb 2007 at 22:26, ben jimenez wrote:

> Finally you asked if you could help. Answer this:
> 
> 1) Are you familiar with HDL languages and which one, Verilog or VHDL.
> Right now most of my work is being done in VHDL. Not sure what Mark is
> doing his in. **no would have to learn. :)



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