[Coco] [Color Computer] Re: POKE 65495,0

[jdaggett at gate.net]

On 3 Feb 2007 at 6:27, James Diffendaffer wrote:

> A version for the CoCo 1/2 would be easy enough.  The Coco3 GIME
> doesn't work the same as the SAM so it probably doesn't need a similar
> program.
> 
************

Both the SAM and the GIME chips have refresh counters and all the necessary 
intergratin to carry out refresh. There is no real need for any ancillary program to 
do refresh to the dram memory. In fact both should do primarily the same 
function as the 4164's and the 41246's both require all 256 rows refreshed within 
4 mS. Also both the SAM and the GIME chip do IDMA. There are other methods 
but IDMA works fine for slower CPU clock speeds of that generation of 
processors. Even True DMA has some limitations as CPU clock speeds get 
higher. SDRAM controllers are nice in that a multiport interface can be built 
around them such that the SDRAM controller now coordinates whom and when 
reads and writes to the SDRAM. 


james 


> >On the Coco 3 the memory array would be a three deminsional array.
> >For 512K size the array would be 256 rows by 1024 columns by 16 bits
> >deep. For the 4164 DRAMs used in the COCO2 it would be 256 rows by
> >256 columns 8 bits deep.
> >
> >Due to the array that the ram is organized on you would startt at
> >$0000 and increment every 256 bytes. Thus $0000 then $0100 and so
> >forth up to $FF00.
> >
> >james
> >
> >
> >
> >On 2 Feb 2007 at 20:45, James Diffendaffer wrote:
> >
> >
> >> Ok, so each read refreshes that entire row in the RAM. So how large
> 
> >> is a row and what addresses would need to be read in order to make
> 
> >> sure all RAM is refreshed periodically?
> 
> >>
> 
> >>
> 
> >>
> 
> >> --
> 
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> 
> >> Coco at maltedmedia.com
> 
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> 
> >
> 
> >
> 
> 
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