[Coco] CoCo 3 512k SRAM Upgrade (Renamed Thread)

[coco at yourdvd.net]

What I was able to determine this morning was the following. Hopefully
this is correct:
the two we signals allow a single byte write to either bank 0 or bank
one. The multi-byte read is accomplished by reading 8 bits on cas low
and then the other 8 bits on cas rise. (note that the service manual
didn't contain the info i hoped - i needed the tech ref manual but
couldn't google one).
The static RAM in use is a 256kx16 with individual access to the high
and low bytes.
So I assumed latching the addresses on the falling edges of the cas and
ras signals would sufficiently demultiplex the address bus. Assuming
that we0 and we1 are always high unless a write is occuring, ANDing
them should be sufficient to generate the WE* signal of the sram and
taking the inverse of that to the OE* should therefore allow the static
ram to enter write mode whenever either of the we* signals goes low,
otherwise it will be in read mode. when the gime is doing a write, the
we0 and we1 signals should be sufficient for the LB* and HB* signals of
the static ram, however, they can't be used for this purpose during a
read, so i thought cas and it's inverse could provide the lb* and hb*
select to the static ram during a read. But i was tired and some of
this info may be flawed. From looking, I didn't see the e clock
available on the memory headers, only two banks of d0-d7, the z-bus,
we0*, we1*, cas, and ras. I assumed the gime might work something like
the sam/vdg (as you said, cpu has the bus on e high and video on e
low). after just the research i did this morning, i would no longer
consider trying to use a 512kx8 sram for this purpose unless i were
going to make a battery backed 2meg board.

> -------- Original Message --------
> Subject: Re: [Coco] CoCo 3 512k SRAM Upgrade (Renamed Thread)
> From: jdaggett at gate.net
> Date: Sun, April 22, 2007 4:12 pm
> To: CoCoList for Color Computer Enthusiasts <coco at maltedmedia.com>
> 
> On 22 Apr 2007 at 7:36, coco at yourdvd.net wrote: > I have the service
> manual in my hands. What I'll do is make a truth > table from the
> access diagrams and then we can work from that. The way > memory
> access is performed is different than I originally thought - I > had
> thought about using a 512Kx8 static RAM because I thought the we0 >
> and 1 signals functioned like r/w* lines, but NOT QUITE :-) -r > >
> **************** They are write enable signals for two banks. james >
> > -------- Original Message -------- > > Subject: [Coco] CoCo 3 512k
> SRAM Upgrade (Renamed Thread) > > From: coco at yourdvd.net > > Date:
> Sun, April 22, 2007 7:24 am > > To: CoCoList for Color Computer
> Enthusiasts  > > > > To Sylvain Rousseau: I've renamed this thread. I
> have been looking > > into your schematic. Now, from a quick research
> of the G.I.M.E. I > > find that a write cycle is as follows: The
> G.I.M.E. writes data by > > BYTE via the we0* or we1* 256k bank
> selects. Whilst a read cycle is > > as follows: The G.I.M.E. reads
> data by WORD, 8 bits via cas low > > followed by latching the next
> 8-bits on cas rise and reading it from > > the latch. (I am using
> ''WORD'' to represent 16-bits, but it's had > > so many meanings over
> the years...) This will help later on in the > > day as I work on
> this. Anyway, your schematic indicates that you are > > using
> negative-edge triggered latches to demultiplex the z-bus. If > > this
> is the case, the inversion of the ras and cas prior to entering > >
> the latches should be removed. However, I need to find the CoCo 3 > >
> timing diagrams, if I had those, I could solve this in a few hours. >
> > Are they online? Perhaps a copy of the CoCo 3 Tech Ref Manual and/or
> > > service manual - if anyone knows of a readily available download
> of > > these, I could solve this in a couple of hours. I work best
> from > > truth tables and timing diagrams rather than schematics. > >
> Theoretically, during a read cycle, both we0 and we1 should be high, >
> > but if there is the slightest chance that this isn't the case, > >
> ANDing the two signals cannot be used to generate the *we signal. > >
> But I need to go search for the timing diagrams. Any info anyone > >
> might have would be appreciated, because CoCo 3 RAM access is > >
> actually amazing that it even works considering one byte of the word >
> > is latched then fed to the gime and finally to the cpu - propagation
> > > delay from hades, I would think... I'll keep digging - rob > > >
> -------- Original Message -------- > Subject: Re: [Coco] Re : Re : > >
> FREE Services For Members Of The CoCoList > at Malted Media > From: >
> > coco at yourdvd.net > Date: Sun, April 22, 2007 5:33 am > To: CoCoList
> > > for Color Computer Enthusiasts > > I see what I believe may be
> some > > potential problems with the schematic > but before I go and
> make a > > fool of myself, I am going to go fetch the > > > data sheet
> for the sram and examine the gime memory timings. I'll > > get > back
> to you in a few hours. -rob > -------- Original Message > > -------- >
> > Subject: [Coco] Re : Re : FREE Services For Members Of > > The
> CoCoList > at > Malted Media > From: Sylvain Rousseau > Date: > > Sat,
> April 21, > 2007 4:22 pm > To: CoCoList for Color Computer > >
> Enthusiasts > > > > Yes, > Mr. Merchberger host it for we at this
> address: > > > > http://zmerch.30below.com/coco/coco3sram.pdf Thank
> you again Mr. > > > > Merchberger. Sylvain ----- Message initial ----
> De : Mark Marlette ? > > > > > > : coco at maltedmedia.com Envoy? le :
> vendredi 20 avril 2007, 13 h 16 > > min > > 11 s Objet : Re: [Coco] Re
> : FREE Services For Members Of > > The > > > CoCoList > at Malted
> Media IIRC there were some level problems in > > your > circuit. I >
> think you posted a .jpg of it. I looked at it > > quickly. > Don't
> totally > remember. Working other designs and > > sometimes they all >
> run together. > Heck maybe it was my levels > > that were off.... :)
> Mark > Quoting > coco at yourdvd.net: > What 512k > > static ram are you
> using? the > first to > hit the scene were > > > semistatic requiring
> something like an > 8ms? > refresh or so (these > > were > hitachi).
> The current ones are > fully > static. The 4464 > > used in the 128k >
> machine use a > bidirectional i/o > line like the > > static rams. The
> 41256 > has a > seperate din and dout > line but > > these are shorted
> together in the > > coco 3 memory circuit. > did > > you account for
> the 256k bank switch? > > > if all else fails you > > > can make one
> of these: > > > > > > >
> ftp://ftp.maltedmedia.com/coco/TUTORIALS/How_To_Upgrade_To_512k_With >
> > out_A_Commercial_Memory_Board.zip > > > > > D?couvrez ce qui fait
> jaser les gens ! Visitez les groupes de > > > > > > > > > l'heure sur
> Yahoo! Qu?bec Groupes. http://cf.groups.yahoo.com/ -- > > Coco > >
> mailing list Coco at maltedmedia.com > > > >
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> 4/21/2007 11:56 AM > -- Coco mailing list Coco at maltedmedia.com
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