[Coco] Re : Re : FREE Services For Members Of The CoCoList at Malted Media
Sylvain Rousseau
surtoutnombliepas at yahoo.ca
Fri Apr 20 21:49:22 EDT 2007
This is the source code I used in my CPLD. I hope I will can to send you a schematic later this weekend.
Thank you all for your help.
Sylvain
MODULE sramupgrade
TITLE '512k sram upgrade'
"Sylvain Rousseau"
"November 18th, 2006"
// Inputs
RAS PIN; " DRAM RAS : Row address strobe
CAS PIN; " DRAM CAS : Colomn address strobe
WE0 PIN; " WE0 : Write enable byte 0
WE1 PIN; " WE1 : Write enable byte 1
ZBUS8 PIN; " ZBUS A0-A8
ZBUS7 PIN; " ZBUS A0-A8
ZBUS6 PIN; " ZBUS A0-A8
ZBUS5 PIN; " ZBUS A0-A8
ZBUS4 PIN; " ZBUS A0-A8
ZBUS3 PIN; " ZBUS A0-A8
ZBUS2 PIN; " ZBUS A0-A8
ZBUS1 PIN; " ZBUS A0-A8
ZBUS0 PIN; " ZBUS A0-A8
// Outputs
WE PIN ISTYPE 'COM'; " WE : Write enable to SRAM
OE PIN ISTYPE 'COM'; " OE : Output enable to SRAM
ADDRH8 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRH7 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRH6 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRH5 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRH4 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRH3 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRH2 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRH1 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRH0 PIN ISTYPE 'REG,BUFFER'; " ADDRH : Address High bits to SRAM
ADDRL8 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
ADDRL7 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
ADDRL6 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
ADDRL5 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
ADDRL4 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
ADDRL3 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
ADDRL2 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
ADDRL1 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
ADDRL0 PIN ISTYPE 'REG,BUFFER'; " ADDRL : Address Low bits to SRAM
HB PIN ISTYPE 'COM'; " HB : High byte enable to SRAM
LB PIN ISTYPE 'COM'; " LB : Low byte enable to SRAM
// Nodes
WEINT NODE ISTYPE 'COM';
// Bus
ADDRH = [ADDRH8..ADDRH0];
ADDRL = [ADDRL8..ADDRL0];
ZBUS = [ZBUS8..ZBUS0];
EQUATIONS
ADDRH.CLK = !RAS; "Stock first part of the address
ADDRH := ZBUS;
ADDRL.CLK = !CAS; "Stock last part of the address
ADDRL := ZBUS;
HB = !WE1;
LB = !WE0;
WEINT = WE0 & WE1;
WE = WEINT;
OE = !(WEINT & !CAS)
END
----- Message initial ----
De : Mark Marlette <mark at cloud9tech.com>
À : coco at maltedmedia.com
Envoyé le : vendredi 20 avril 2007, 13 h 16 min 11 s
Objet : Re: [Coco] Re : FREE Services For Members Of The CoCoList at Malted Media
IIRC there were some level problems in your circuit.
I think you posted a .jpg of it. I looked at it quickly. Don't totally
remember.
Working other designs and sometimes they all run together. Heck maybe
it was my levels that were off.... :)
Mark
Quoting coco at yourdvd.net:
> What 512k static ram are you using? the first to hit the scene were
> semistatic requiring something like an 8ms? refresh or so (these were
> hitachi). The current ones are fully static. The 4464 used in the 128k
> machine use a bidirectional i/o line like the static rams. The 41256
> has a seperate din and dout line but these are shorted together in the
> coco 3 memory circuit. did you account for the 256k bank switch?
>
> if all else fails you can make one of these:
> ftp://ftp.maltedmedia.com/coco/TUTORIALS/How_To_Upgrade_To_512k_Without_A_Commercial_Memory_Board.zip
>
>
>
>> -------- Original Message --------
>> Subject: [Coco] Re : FREE Services For Members Of The CoCoList at
>> Malted Media
>> From: Sylvain Rousseau <surtoutnombliepas at yahoo.ca>
>> Date: Fri, April 20, 2007 9:41 am
>> To: CoCoList for Color Computer Enthusiasts <coco at maltedmedia.com>
>>
>> I tried to made one myself (512k static ram for CoCo3) last winter but
>> it don't works. I got an oscilloscope last week. I expect to
>> investigate it soon. I hope it will works because I don't have a 512k
>> CoCo3, only 128k so I can't try the new Sockmaster port of DonkeyKong
>> :( I use a Lattice CPLD (isplsi1016e) to demux the Gime address bus.
>> Sylvain ----- Message initial ---- De : "coco at yourdvd.net" À :
>> CoCoList for Color Computer Enthusiasts Envoyé le : vendredi 20 avril
>> 2007, 11 h 24 min 24 s Objet : Re: [Coco] FREE Services For Members Of
>> The CoCoList at Malted Media You could actually modify the refresh (i
>> think it has something to do with a cas before ras type refresh, but i
>> can't remember) and make them work if you wanted to add some extra
>> circuitry. I'll get into my box of simms and sort out all of the
>> 256's. I was thinking about attempting to demultiplex the gime address
>> bus so it could support 512k fully static rams (about 17 bucks each),
>> but i haven't looked into it enough to see if it is a possibility. the
>> gime is designed for dual 256k banks using a 256 cycle refresh. One
>> bank is for even addresses, the other odd addresses. The banks are
>> accessed by the two we signals. I though perhaps i could use cas and
>> ras to latch the addresses and use the we signals to generate the
>> upper address bit and make it work, but again, i haven't looked into
>> it fully. -r > -------- Original Message -------- > Subject: Re:
>> [Coco] FREE Services For Members Of The CoCoList at Malted > Media >
>> From: Roger Merchberger > Date: Fri, April 20, 2007 8:08 am > To:
>> CoCoList for Color Computer Enthusiasts > > Rumor has it that
>> coco at yourdvd.net may have mentioned these words: > >i've got the 3 8
>> and 9 chip versions. My question is, do i need to > >verify that they
>> are 256k or if i send larger simms (they're all 30 > >pin), as long as
>> they are 8/9 chip, will they work as 256k simms in > >your card? i can
>> plug up and old 486 and verify them if i need to. I > >bought a lot of
>> them because i thought i might need them one day. > >Bought all i
>> could find regardless of mem size, but i want to make > sure >i send
>> useable simms. -r Only the 8 or 9 chip 256K Simms (the > 9th chip is
>> parity, which is ignored) will work on a CoCo - Mark > already
>> educamated me on that fact in the past. It all has to do with > DRAM
>> timing issues, and the 1Mbit chips just aren't refreshed the same > as
>> the 256kbit chips. I have 80 1Meg 9-chip 30-pin Simms available > from
>> an old DEC 3-processor 486 server, it rather sucks that I can't > use
>> any of them for any of my CoCo (or other classic) equipment. I > wish
>> I had enough knowledge to make 'em into a nice 80Meg Solid State >
>> Drive ... IMHO that would be kewl beyond belief! Laterz, Roger "Merch"
>> > Merchberger -- Roger "Merch" Merchberger | Anarchy doesn't scale
>> well. > -- Me zmerch at 30below.com. | SysAdmin, Iceberg Computers --
>> Coco > mailing list Coco at maltedmedia.com >
>> http://five.pairlist.net/mailman/listinfo/coco -- Coco mailing list
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>
>
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