[Coco] Coco ProtoType Board

[jdaggett at gate.net]

On 2 Sep 2006 at 10:37, Mike Pepe wrote:

> Hi James,
> 
> > 2) some form of flexible address decoding included along with buffering. It is still 
> > unclear as to whether just the Coco 3 I/O range be flexible or also the range from 
> > $C000 to $FFDF also be included. 
> 
> I think the PLD would be nice, but overkill.
> 
> It really depends on how much granularity everyone wants. My guess is 
> that an 8 or 16 byte block would probably be sufficient. That could be 
> done with a 74x133, some inverters, and a jumper block to set the X 
> digit in $FFXY. The 13th input could be the E clock to gate the signal.
> 
> If more granularity is needed, a 74x85 or 74x688 could do. It would only 
> require 2 chips, and if you're going to use SMT they would be extremely 
> small. (though I'm oldschool and prefer through-hole on this)
> 
> 
> -Mike
> 
****************

Mike 

The CTS line already gives you a base decode signal for any address between $C000 and 
$FFDF/$FFEF on the Coco3. That can be the enable signal for any 
ROM/EPROM/EEPROM located at that address. Decodeing the I/O range of $FF00 to 
$FF7F requires an eight input and gate for A8 to A15 along with a 4 to 16 decoder for A4 to 
A7. Then A0 to A3 can be used to select any individual address in a block of 16 addresses. 

Just to do user selectable address decode will require the minimum of three discrete ICs. 
Regardless of whether they are surface mount or th rough hole package. An LS245 is then 
needed for the data buss and several LS367 chips are needed for straight buffers for the E, 
Q,  R/W FIRQ, IRQ and other lines. 

I am well aware of the issues regarding PLDs for design. FOr hobbiest the Xilinx 95xxXL 
series of CPLDs offer a better cost factor over older CPLDs . Newere ones have issues with 
not being 5 Volt tolerant and that is by far a major concern in any choice of PLDs. 72 
macrocell devices come in th ree packages that are potential for our needs. A 44 pin PLCC, 
a 84 pin PLCC and a 100 pin TQFP.  First investigation on the 44 pin PLCC package 
eliminates that from choice.  There are at a minimum of 30 inputs on a package that has 
only 36 total usable. The 84 pin PLCC has more usable I/O pins but requires at least 35mm 
x 35mm board space. If you want the parrt socketed, add at least another ten mm per side 
for the board area. Remember the board is only 100mm x 150mm. Now a 100 pin TQFP 
device  only requires 16mm x 16mm. Half that of the 84 pin PLCC. Both the 84 pin PLCC 
and the 100 pin TQFP p[ackage has suitable I/O pins for our needs. One last advantage of 
a TQFP package over a PLCC is cost. TQFP packaging costs are cheaper and so the cost 
of the part is less for equal density of CPLDs. 

Now for one disadvantage of the PLD over discrete logic. It will require the knowledge of 
some form of HDL programming language. CPLDs  are far more easier to program than the 
older  PLA devices due to the lack of IP (intelectual Propoerty) on how to program them. 
Instead the IP is in how the data file is encoded for CPLDs. HDL software is free and runs 
on both Windoze and Linux. Cost wise a CPLD is about equal  in the number of logic gates. 
A CPLD can also be designed to be far more flexible than that of descrte ICs. 

I really don't think a CPLD is an over kill. It does everything that we would need. It offers 
some form of alteration without having to relayout a new PCB. The one goal of this project 
is to do only one pass of PCB design. 

just my opinion
james