[Coco] Dynamic RAM Q

[Richard Atkinson]

Hi Phill,

Good to see another UK person on the list!

Your best bet may be to make A8 and A9 functions of the 14.3MHz SAM clock,
as well as or instead of E and/or Q. What you're trying to do is replicate
the internal state machine inside the 6883 SAM, so that your A8 and A9 lines
change state on the same 14.3MHz cycle as the Z0-Z7 lines do.

There are a number of different ways you could do this. Firstly you could
make a purely digital finite state machine as described above, using the
14.3MHz clock source. It may well need some buffering to drive your circuit;
the SAM oscillator circuit isn't expecting to drive anything other than the
crystal / SAM combination.

An alternative would be to observe the transitions of Z0-Z7 on an
oscilloscope relative to the edges of one of the other clocks, for example E
and/or Q. If there is a fixed timing relationship between them, such that
the transitions on Z0-Z7 lag a known edge on E and Q, you could generate a
select signal for your multiplexers from a suitably delayed version of that.
The SAM datasheet may give guaranteed values for such timing. This may
involve some combinational logic and some time delay elements such as RC
networks. This might not be as 'pure' or 'neat' a solution as above, but it
avoids using the 14.3MHz clock (and having to clock your CPLD that high).

Have you thought about what to do on VDG cycles as well as CPU cycles?

Richard


On 10/6/06, Phill Harvey-Smith <afra at aurigae.demon.co.uk> wrote:
>
> Hi CoCo/Dragon friends,
>
> This may be a little long and rambling, but bear with me.....
>
> I am currently working on a memory expansion board for the CoCo 1/2 &
> Dragon computers, that will hopefully allow me to have up to 1 MB of
> RAM, using an old PC 1MB SIMM, as I have a whole box of these. I
> currently have it emulating the Extra ram part of the Dragon Plus
> expansion system that gave the Dragon an extra 64K of ram that could be
> paged into the bottom 32K of the memory map. This seems to work ok.
>
> Currently I have the Z0..7 lines from the SAM connected to A0..7 on the
> SIMM, the additional A8..11 from the SIMM are connected to a CPLD, so
> that I can toggle the extra address lines as needed. Currently the logic
> in the CPLD consists of a latch that outputs extra values to these lines
> to page in the extra RAM. The CPLD is also connected to the 6809
> Address & Data busses, as well as E,Q, R/W, WE etc. I will be adding a
> small SRAM to act as the DAT, as was done in the Dragon Beta prototype,
> I guess this is buried in the GIME in the CC3.
>
> My (possible) Problem, is that for the next stage to fully address the
> 1M, I will need to be able to put different values on A8 & 9, for Row
> and column. However the diagrams on all the data sheets I have seen seem
> to suggest that the address lines need to be setup before the RAS or CAS
> transition and remain stable afterwards.
>
> However if this is the case there will be a problem, as I will need to
> switch the lines between the RAS and CAS transitions, which could be a
> problem, as there does not seem to be any signal I could utilise to make
> this switch.
>
> The other thing I did notice from the data sheet for the chips on my
> SIMM (HYB511000), is that the setup time for RAS and CAS has a minimum
> of 0, the important thing seems to be the hold time, after the RAS or
> CAS transition, so it would seem from this that I could just us a
> combination of the RAS and CAS signals to decide which bits I need to
> output. So :-
>
> RAS     CAS     A8..9
> 1       1       high Z
> 0       1       Row bits
> 0       0       Col bits
> 1       0       Col bits.
>
> I have done a brief test where I output 00, for the row bits, and the
> values from my latch for the Col bits and this seems to work.
>
> I know some of the other people on this list have worked with things
> like this before, and may be able to shed some light on this.
>
> BTW thanks whoever it was that suggested using CAS before RAS to
> refresh, it has really made this thing MUCH easier, as I can just swap
> RAS and CAS when E and HS are both low, and fakeup RAS from Q (as CAS is
> suppressed by the SAM for refresh cycles).
>
> One final curious thing about this setup is this, if I turn the machine
> on, type a 2 line 10 Print "Phill was here "; 20 Goto 10 type program,
> and run it, it runs. If I then turn the machine OFF for 5 seconds and
> then back on again, and type RUN it's still there !!!! I have also
> noticed this on some CoCo 1/2 models too, so much for Dynamic ram
> needing to be refreshed :) :) :)
>
> Cheers,
>
> Phill.
>
> --
> Phill Harvey-Smith, Programmer, Hardware hacker, and general eccentric !
>
> "You can twist perceptions, but reality won't budge" -- Rush.
>
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