[Coco] Dynamic RAM Q
afra at aurigae.demon.co.uk
Sun Oct 8 10:51:08 EDT 2006
Richard Atkinson wrote:
> Hi Phill,
> Good to see another UK person on the list!
Yeah I'm on the Dragon one too, dunno if you are a CoCo or a Dragon
> Your best bet may be to make A8 and A9 functions of the 14.3MHz SAM
> clock, as well as or instead of E and/or Q. What you're trying to do
> is replicate the internal state machine inside the 6883 SAM, so that
> your A8 and A9 lines change state on the same 14.3MHz cycle as the
> Z0-Z7 lines do.
Yes this is what I am trying to do, so that I effectivly increse the
size of the memory the SAM can address.
> There are a number of different ways you could do this. Firstly you
> could make a purely digital finite state machine as described above,
> using the 14.3MHz clock source. It may well need some buffering to
> drive your circuit; the SAM oscillator circuit isn't expecting to
> drive anything other than the crystal / SAM combination.
Yeah I did wonder about that though it would make things a little more
> An alternative would be to observe the transitions of Z0-Z7 on an
> oscilloscope relative to the edges of one of the other clocks, for
> example E and/or Q. If there is a fixed timing relationship between
> them, such that the transitions on Z0-Z7 lag a known edge on E and Q,
> you could generate a select signal for your multiplexers from a
> suitably delayed version of that. The SAM datasheet may give
> guaranteed values for such timing. This may involve some
> combinational logic and some time delay elements such as RC networks.
> This might not be as 'pure' or 'neat' a solution as above, but it
> avoids using the 14.3MHz clock (and having to clock your CPLD that
When I looked at it with my logic analiser, it did seem like the video
clock could possibly be used as it seemd to rise just before RAS, and
fall just before CAS. However I have been reading some RAM data sheets
which seem to suggest that the RAM latches the address lines shortly
after the fall of RAS and CAS, in this case I can just use these signals
to gate the Z lines, if I have a fast enough CPLD, which I believe that
> Have you thought about what to do on VDG cycles as well as CPU
Yeah at the moment, Z8 and above are forced to 0 when the E clock is
low, which of course means that the VDG is limited to the first 64K, but
it also keeps things simple for the time being, I may later if my CPLD
has enough free logic space add an offset reg for the VDG which would
allow it to address the whole 1M.
Phill Harvey-Smith, Programmer, Hardware hacker, and general eccentric !
"You can twist perceptions, but reality won't budge" -- Rush.
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