[Coco] Re : 512KB SRAM upgrade
lamune at doki-doki.net
Fri Nov 24 11:06:13 EST 2006
jdaggett at gate.net wrote:
> I seriously doubt that the WE0 and WE1 lines remain high suring refresh. In order
> to do a refresh the row address is placed on the DRAM address lines and then the
> RAS and WE lines are pulled low.
Refresh cycles are reads, not writes. Just google and download any
4164/41256/etc datasheet and check the refresh timing diagrams.
The refresh cycles would be pointless but probably not dangerous.
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