[Coco] Re: CoCo video? (CoCo4)

[jdaggett at gate.net]

On 4 Mar 2006 at 19:50, KnudsenMJ at aol.com wrote:

> Oh yes, we had a couple of Xilinx parts and programmers to work on  them. 
> SOmeone was right -- when you finally integrate all the subsystems  on the
> final chip, all kinds of extra gates and speed losses show up due to 
> overhead.  So do budget for that. --Mike K.

******

What I am seeing is that there is often more loss in speed due to routing issues 
within the FPGA. That probably is the one weakness of some FPGAs. You can have 
two levels of gates and only a propogation of 2nS in the logic. Then can add as 
much as another 3nS in routing delays. A real pain. 

Another thing that is a problem with HDL is the unitentional inference of latches. 
There is a trick to learn how not to get extra latches. I have also seen that not all 
VHDL compilers and synthesis tools are equal. VHDL compilers are somewhat 
dumb. While some compilers and synthesis tools try to build in some smarts, you 
best make sure that critical logic has all the right constraints. It does pay to become 
proficient with the set of VHDL tools that you plan to use the most. Also it is easy to 
write code in VHDL that is either simulatable or synthesizable. Writing VHDL to do 
both takes time and technique. VHDL probably has more issues than does Verilog. 
That is probably more why Verilog is accepted along with it's similarity in syntax with 
C. 

james