[Coco] [color computer] Just imagining...
lamune at doki-doki.net
Tue Jan 31 22:12:01 EST 2006
Larry Osborne wrote:
> There was one written IIRC. It was OS-9 Level 3 for the GIMMIX 3
> Computer. It was often advertised in old Rainbows.
> Gimmix OS-9 Level One was essentially what you see with a CoCo 1 or 2
> (64K) but with better hardware and IO support.
> Gimmix OS-9 Level Two was essentially what you see with a CoCo 3 (More
> Memory than the 6809 could address directly with 4K blocks rather than
> 8K blocks as in the CoCo3) with much better hardware support for the IO
> Gimmix OS-9 Level Three had no CoCo equivalent at all; rather you had
> several (2 3 ?) 6809's again with much better internal and IO support.
> If you can find someone who has an old one (esp if it is still working)
> you might be able to see how the software handled it. I suspect though
> that the internal hardware was probably the most important item in
> making it work with the software along but barely aware of it as I don't
> see how a 6809 could possibly function with another 6809 any one
> circuit. I would imagine that Memory Management kept the 6809's from
> interacting directly in any way.
> If my memory is in error my apologies.
> Larry Osborne
I had a couple of ideas. One that comes to mind is to simply let an
additional CPU to utilize the bus when the primary is idle or busy
executing an internal instruction. That sounds like what Phill mentioned
before- a circuit that uses TSC/LIC/BS/BA lines to arbitrate the bus
(6809E was designed with this in mind)
The IDMA concept is, of course, what the 6847/6883 combo in the CoCo
does. E high=CPU, E low=VGA. You can substitute another 6809 to operate
during E low, or a 6844 DMA controller, etc. Unfortunately this won't
work in a CoCo since that dead time is taken up by the VDG.
My plan was to break one cycle into 4 pieces. essentially a 4 phase
system where each component lags 90 degrees. 3 CPUs can get 3/4 of the
cycle and the last can be for video/refresh if DRAM is used.
Unfortunately this needs a lot of latches and 60ns memory!
Probably something that could be hacked into a FPGA/CPLD array.
Anyway, that's what I was thinking.
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