[Coco] [color computer] Just imagining...
jdaggett at gate.net
jdaggett at gate.net
Tue Jan 31 18:12:55 EST 2006
Small more modern FPGAs are now approaching the $10 range. Some of the older small
FPGAs are still a bit pricy. In comparison single unit price of a Spartan 2 15K gate versus a
Spartan 3 50K gate is virtually even. $10.89 for the older part and $10.10 for the newer part.
More capacity and not much difference in cost.
CPLDs are even still cheaper. The major problem in usig FPGAs and CPLDs is most are
designed for 3 volt logic levels. There are still some that have 5 volt tolerent inputs. You can
do a lot in some of the CPLDs and small FPGAs like MMUs. UARTS, IDE interface, SPI,
PS2 interface, and even a simple video unit. One approach is to use the current 6x09 and
three or four CPLDs or a couple of small FPGAs. Or use one big FPGA.
The idea of going to a Spartan 3 is this device ranges from $25 for a 200K gate equivalent
to about $55 for a 1 million gate equivalent. A XC3S1000 (1 million gate equivalent) can
house the complete Coco3 with room to spare. You might even be able to squeeze the
whole Coco 3 into XC3S400 (400K gate). With a 1.5 million gate Spartan 3, one can put the
whole Coco 3 in one plus a Math Coprocessor. Everything could run at about 25 MHz also
Doing an imagining session, one can let their ideas take them anywhere they want. I
currently have access to a 6809 core that is supposed to run at 12 MHz. I have a Spartan
2E (300K gate equivalent) development board and the CPU core will take up about 2/3rds
of it. An improved GIME with expanded video takes ups about 50K gates. Two UARTS and
a parallel port and IDE should fit in the remaining with maybe some room left over. Alot will
determine how complex the UARTS will be.
On 31 Jan 2006 at 20:36, Phill Harvey-Smith wrote:
Date sent: Tue, 31 Jan 2006 20:36:20 +0000
From: Phill Harvey-Smith <afra at aurigae.demon.co.uk>
To: CoCoList for Color Computer Enthusiasts <coco at maltedmedia.com>
Subject: Re: [Coco] [color computer] Just imagining...
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> Though I guess the thing that complicated this case was the MMU
> implemented in LS+a few pals+some static ram. Guess if you where doing
> it now, you could get away with just the major chips a couple of
> CPLDs/FPGAs, and do it in less than 20 chips :) (I'm asuming you don't
> want to bury the whole thing in a big expensive FPGA).
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