[Coco] CoCo 3 DMA controller

[jdaggett at gate.net]

Mike 

Cycle stealing will work. What will make it work better is to increase the tasks to 
the GIME chip and then each DMA channel could be assigned its own  heap 
storage. This would help minimize the problems with context switcing and thus 
loose what advantage any DMA gains. 

Then again this all would require tighter integration of the processor, GIME chip 
and DMA controller.

james

On 27 Aug 2006 at 21:30, Mike Pepe wrote:

> Warning: esoteric technical details below.
> 
> Folks,
> 
> Would there be any interest in a DMA controller for the CoCo?
> 
> I had a thought and just checked the 6809E datasheet for confirmation.
> 
> The 6809E will output an AVMA signal when the CPU does not need the bus 
> in the upcoming cycle.
> 
> I was thinking that these "dead" cycles could be hijacked by a DMA 
> controller and used- for something.
> 
> If you were to latch this signal (which precedes the E clock high 
> transition, you could then feed it into the TSC pin which tri-states the 
> address & data busses and R/W. This effectively disconnects the CPU from 
> the CoCo hardware.
> 
> If you then activated your DMA controller during this cycle, you could 
> do a read or write and then release the bus at the end of the cycle. The 
> CPU should continue running unimpeded. This would not affect program 
> speed at all, since it would just hijack dead cycles.
> 
> The DMA controller could just be a simple set of counters and latches. 
> During one cycle, do a read of address X. The next DMA cycle, you write 
> that to address Y. Increment and repeat.
> 
> Seems pretty simple to implement.
> 
> Some downsides to this:
> 
> 1- you can't tell how much bus bandwidth would be available for DMA. 
> Using it for something critical might be a problem. The amount of 
> available cycles depends heavily on what the CPU is running.
> 
> 2- it would use the same address mapping as the CPU. If you change your 
> memory blocks, your DMA would read/write to the wrong place.
> 
> I thought about problem 2. If the DMA controller had 18 bit 
> counter/registers, you could also then hijack CAS/RAS on the 512k board 
> and directly read and write anywhere in the map, regardless of the CPU's 
> memory space. Cool, but more technically challenging.
> 
> It would also be an interesting project, though I wanted to throw it out 
> there to see if there's really any practical use for such a thing that 
> you guys can think of.
> 
> It would be kind of neat to really scroll the text screen in hardware. 
> Or to scroll a bitmapped "pmode 4" text screen. That's all I can think 
> of at the moment.
> 
> -Mike
> 
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