[Coco] Timing problem with the CoCo and the WD1773 ?

[Warren Hoslet]

>Robert Gault wrote:
>...
>
>The correct explanation of the BLOB (there are others) is on RTSI.
>www.rtsi.com/OS9/OS9_6X09/TXT  BlobStop.lzh   It is unfortunate that this 
>paper is under OS-9 as the problem has nothing to do with OS-9 but rather 
>is a Western Digital controller problem.
>
-
Thanks for pointing me to that information. I knew I had read about it 
somewhere. However, after reading it again and comparing it with my own 
findings, I now believe that it is not completely accurate.

The paper suggests that the problem does not seem to plague systems running 
at 0.89 mhz, but I can reproduce it quite easily on both a CoCo 1 and 2 
running at normal speed.

It also states that the problem occurs when the instruction which reads the 
status register is executed at an odd address. This is not entirely true. If 
the instruction used is two bytes in length (such as BITA ,U) and it is 
executed at an odd address where the two low bits are 01, then the problem 
does occur. If it is executed at an odd address where the two low bits are 
11, then it works fine. When a three byte instruction (such as BITA >$FF48) 
is used, then the problem only occurs if it is executed at an EVEN address 
where the two low bits are 00.

This seems to suggest that it is not the address of the instruction which 
performs the test that is critical, but rather the address of the 
instruction which follows it. When the two low bits in the address of the 
following instruction are 11, you've got trouble.

My theory is that the FDC logic which determines when the DRQ should be 
cleared is happening as the 6809 is preparing the address bus to fetch the 
next instruction opcode. When it sees 11 on the two low bits of the address 
bus, it thinks that a read of the Data Register has occurred, so it clears 
DRQ. But this theory has a problem: Why does an actual read of the Data 
Register seem to work correctly at any address?

- Warren