[Coco] [Color Computer] USB project

[jdaggett at gate.net]

James

To some extent that is what I found in learning VHDL on my own. All the examples 
are real simple or here is a 32 bit risc CPU with 4 levels of pipeline instruction cue 
in one package. What h elped me is my background in logic design. In a couple of 
books I picked up states the VHDL describes behavior or structure. Thus one can 
write code to say take these signals in and produce this output. Or you can even 
describe the gate level logic and how to hook them up. It is a very versitle language 
and how you write code candetermine how big the logic actually is. Once learing 
VHDL and its syntax, the hard part is to learn to write code that synthesizes 
compact logic for high speed. Not all synthesis tools are created equal. All some 
designs for synthesis will not simulate wel on some simulators. That is all in the 
learning process.  

Wher eI h ave found a lot of  help in understanding VHDL is in the news group: 

comp.language.vhdl

In that group there are about a dozen very good people that know VHDL well. Top 
of the list in my opinion is Ray Andarka. ALso what is nice is two application 
engineers from Xilinx and Altera also monitor that group. They are very helpful 
when code is directed at their specific products. 

The code I supplied will synthesize I know in a FPGA and since it is no more that 
product term equations it should synthesize in a CPLD since that is basically how 
they are programmed. 

The code is for the IO sectio of the GIME chip section. I took the liberty to bring out 
a IO chip select for each range of 16 bytes from FF00 to FF90. All I have left to do 
now is:

1) do the register select file 
2) SCS signal out
3) The registers to be backward compatible with the SAM chip 
4) Extend the MMU task registers to 16 tasks
5) and mesage the 640x480 VGA code to work with the linear address generator.

I initially plan to use John Kent's 6809 CPU core, which runs at 12.5 MHz. With that 
and the new GIME core, Most of the function of the COCO 3 should drop into one 
FPGA.  Later I will modify the CPU core to include 6309 instruction sets and see if I 
can speed the whole design up to 25 MHz.  

james


On 30 Jul 2005 at 13:08, James Diffendaffer wrote:

To:             	ColorComputer at yahoogroups.com
From:           	"James Diffendaffer" <jdiffendaffer at yahoo.com>
Date sent:      	Sat, 30 Jul 2005 13:08:55 -0000
Subject:        	Re: [Coco] [Color Computer] USB project
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> James, thanks for the VHDL.  I spent a half hour looking through
> examples on the web and none did what I wanted.  They were either too
> simple or "here is a complete CPU in VHDL". That looks pretty simple
> so the CPLD project might not be so bad. Really, I just need the
> proper examples to figure out VHDL.  I don't have problems with the
> logic. A VHDL version of USB interface just needs the extra pins
> defined, a little logic and it's done.  Too simple.