[Coco] HD63x09 Question

[Robert Gault]

You are correct in your assumptions. Be careful with the MUL and DIV 
instructions as there are very unexpected results from overflow. In 
fact, the DIV instructions seem not to work at all if an overflow would 
be the result.

It is possible to write code that uses MULD to get an unsigned answer 
but the overhead may make it not worth the effort.

*Unsigned 16by16 bit multiply
*ENTER: numbers in regD & REGX
*EXIT: regD&X unchanged, answer in regY&U

MUL16	PSHS	D,X
	MULD	2,S
	TFR	D,Y
	TFR	W,U	regY&U now contain signed answer
	BNE	NOTZRO
	TSTW
	BEQ	ZRO
*Convert signed answer to unsigned. Only regY (MSW) will change.

*If answer is Neg, add positive multipliers
NOTZRO	BPL	MULP2
	PULS	D,X
	TSTA
	BMI	MB1
	ADDR	D,Y
MB1	CMPX	#$8000
	BHS	MC1
	ADDR	X,Y
MC1	RTS

*If answer is Pos, add negative multipliers
MULP2	PULS	D,X
	TSTA
	BPL	MB2
	ADDR	D,Y
MB2	CMPX	#$8000
	BLO	MC2
	ADDR	X,Y
MC2	RTS

jdaggett at gate.net wrote:
> to the 6309 experts:
> 
> I recently obtained 4 HD63C09EP chips and was looking at doing a 
> project with them. I did a Google search and found the original post 
> to comp.sys.m6809 group by Hirotsugu Kakugawa. Between that 
> memo and Chet Simpson's technical manual I have some needs to 
> confirm what I suspect:
> 
> 1) that the increased instruction set is available in either "emulated" 
> or "native" modes and that 
> 
> 2) the MULD and the DIVD and DIVQ instructions due signed math 
> and not unsigned!
> 
> This seems odd as the MUL instrtuction of the 6809 is unsigned. IF 
> the new math opcodes are indeed signed math then I will  have to 
> do some extra manipulation since  I am doing unsigned math.
> 
> 
> james
>