[Coco] CoCo hardware cycle

[Fedor Steeman]

Hello all,

I posted this message before, but I guess it got swamped by other messages,
so I am posting it again.

I am trying to get a reasonably accurate picture of what is going on inside
the CoCo1/2 in terms of hardware processes. I am especially interested in
how hardware components like the CPU, SAM, and VDG communicate. Hence, I
have written a preliminary use case to describe the sequence of events
during a regular CPU cycle on the basis of descriptions in several books and
articles. Now I  am convinced this use case is flawed so I wanted to hear
whether there were any hardware buffs that could help me getting it right.

Here it comes, please feel free to edit:

Use Case: Normal Hardware Cycle
1. VDG gets byte from memory address accessed by SAM
2. SAM sends a high Q-signal to the CPU
3. CPU program counter register is incremented
4. SAM accesses videoRAM at the address specified by... ?some internal
register
5. VDG gets byte at RAM address and sends data on to video signal generator
6. VDG increments ?some internal register in SAM
7. SAM sends a high E-signal to 6809
8. 6809 accesses RAM at the address specified by the Program Counter
register
9. RAM address sends byte to 6809 (6809 reads RAM address byte)
10. SAM sets Q-signal low
11. 6809 acts on byte (executes instruction)
12.SAM sends a low E-signal (to 6809)
13.repeat steps 1...13 until power is cut

Thanks in advance!

Fedor Steeman