[Coco] Re: [Color Computer] Sam/Ram question.

[jdaggett at gate.net]

Phil

I do believe that etting the M0 and M1 bits will also disable the mux for 
refresh counting. Therefore the refresh count is never outputed to the Z 
Buss. 

Also which SRAM are  you using? What density?

james
 

On 28 Dec 2005 at 16:27, Phill Harvey-Smith wrote:

To:             	ColorComputer at yahoogroups.com
From:           	Phill Harvey-Smith <dragon at aurigae.demon.co.uk>
Date sent:      	Wed, 28 Dec 2005 16:27:17 +0000
Copies to:      	Subject:        	[Coco] Re: [Color Computer] Sam/Ram question.
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> Mike Pepe wrote:
> > Gene Heskett wrote:
> >> On Wednesday 28 December 2005 06:47, Phill Harvey-Smith wrote:
> > ...what Gene said is true, though some CoCo models don't have resistors 
> > there, they instead have small ferrite beads. I don't suspect that would 
> > cause the problem you're seeing (though it might)
>  >
> > Have you modified the CoCo ROM to put the SAM into SRAM mode? Maybe all 
> > the superfluous refreshing is causing some glitching or timing problems.
> 
> No, trying to make a module that will work as a straight replacement, 
> though my PLD, does suppress reads when both /HS and E are low, which is 
>   when acording to the SAM datasheet the refresh takes place.
> 
> Could be of course that my timing is still slightly out....
> 
> Phill.
> 
> 
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