[Coco] 6309 Division instructions

[Robert Gault]

Is that a typo? Why would regW be involved with DIVD?

jdaggett at gate.net wrote:

> Tim 
> 
> from the 6309 documentation I h ave the DIVD does a 16 bit by 8 
> signed division. The contents of W is divided by memory byte and 
> the quotient is stored in W and the modulo (remainder) is in D. 
> 
> This yields +32,767/-32,768 divided by +127/-128 ranges. 
> 
> 
> Initial thoughts on how to get an overflow condition would mean the 
> modulo would overflow or the divisor is "one"?
> 
> james
> 
> On 1 Aug 2005 at 20:15, tim lindner wrote:
> 
> To:             	coco at maltedmedia.com (CoCo Mailing List)
> From:           	tlindner at ix.netcom.com (tim lindner)
> Date sent:      	Mon, 1 Aug 2005 20:15:58 -0700
> Organization:   	Computers Suck, Inc.
> Subject:        	[Coco] 6309 Division instructions
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>>I was testing the division instructions against my 6309 core (in MESS)
>>and found something unusual.
>>
>>My Burke & Burke 6309 documents say that result of DIVD is a signed
>>8-bit value in register B and an unsigned remainder in register A.
>>
>>Further more it says that if the quotient overflows, the value of A
>>and B will be unchanged and the V condition code will be set.
>>
>>But this is not exactly the behiavior I am seeing on real hardware.
>>
>>What I am seeing is a sort of two stage overflow. If the quotient
>>doesn't fit in an signed 8 bit container but would fit in a unsigned 8
>>bit container, then the correct absolute value is wirrten to B and the
>>V condition code is set.
>>
>>If the value overflows an unsgined container, the registers A and B
>>set to the absolute value the the orginal numerator and the V
>>condition code is set.
>>
>>I have not seen this behiavor described anywhere and I would be
>>interested in other peoples thoughts on it.
>>
>>-- 
>>tim lindner
>>tlindner at ix.netcom.com                                   Bright
>>
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> 
> 
> 
>