[Coco] 6309 Division instructions

jdaggett at gate.net jdaggett at gate.net
Tue Aug 2 16:52:23 EDT 2005


Robert

I quote from the 6309 Technical Reference Guide by Chet Simpson

"The DIVD (16 bit by 8 bit) instruction does a signed divide of
the contents of the D register with a value from memory (or in
direct mode). The signed result is stored with the quotient
in W and the modulo (remainder) in D."


Now if this is in error, then I am in error. From your posting then the above
document must be in error.


>From your example it appears that reg B has the quotient and reg A has the

remainder. If this is so then there is something else going wrong in the instruction.
Since the last time I checked, division of a negative integer by a positive interger
should yield a negative integer quotient. According to reg A results this is a positive
number.

$BCEF signed integer should be a negative -15599. Divide that by 24 and you get
-649 quotient of hex $8289 in word format.

What still bothers me is the results still don't add up to being close.

james

On 2 Aug 2005 at 13:39, Robert Gault wrote:

Date sent: Tue, 02 Aug 2005 13:39:54 -0400
From: Robert Gault <robert.gault at worldnet.att.net>
To: CoCoList for Color Computer Enthusiasts
<coco at maltedmedia.com>
Subject: Re: [Coco] 6309 Division instructions
Send reply to: CoCoList for Color Computer Enthusiasts
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> Not on my system running under Disk Basic. If regD is loaded with any

> number then DIVD # has no effect at all on regW but only regA and

> regB. If your test was made under OS-9, the results may be different

> and possibly misleading.

>

> For example using EDT6309 my version of EDTASM the following:

>

> START LDD #$BCEF

> DIVD #24

> SWI

> END

> gives

> A=$43 B=$11 DP=00 CC=$8A =ENV

> X=0000 Y=0000 U=0000 S=$1579

> PC=$56E2 V=0000 E=00 F=00

>

> Change to LDD #24 and regA=00 regB=01 CC=$81 =EC and regW is still

> 0000.

>

> jdaggett at gate.net wrote:

> > Sorry was a typo. Contents of D. W and D are the results.

> >

> > james

> >

> > On 1 Aug 2005 at 23:48, Robert Gault wrote:

> >

> > Date sent: Mon, 01 Aug 2005 23:48:46 -0400

> > From: Robert Gault <robert.gault at worldnet.att.net>

> > To: CoCoList for Color Computer Enthusiasts

> > <coco at maltedmedia.com>

> > Subject: Re: [Coco] 6309 Division instructions

> > Send reply to: CoCoList for Color Computer Enthusiasts

> > <coco at maltedmedia.com>

> > <mailto:coco-

> > request at maltedmedia.com?subject=unsubscribe>

> > <mailto:coco-

> > request at maltedmedia.com?subject=subscribe>

> >

> >>Is that a typo? Why would regW be involved with DIVD?

> >>

> >>jdaggett at gate.net wrote:

> >>

> >>

> >>>Tim

> >>>

> >>>from the 6309 documentation I h ave the DIVD does a 16 bit by 8

> >>>signed division. The contents of W is divided by memory byte and

> >>>the quotient is stored in W and the modulo (remainder) is in D.

> >>>

> >>>This yields +32,767/-32,768 divided by +127/-128 ranges.

> >>>

> >>>

> >>>Initial thoughts on how to get an overflow condition would mean the

> >>>modulo would overflow or the divisor is "one"?

> >>>

> >>>james

> >>>

> >>>On 1 Aug 2005 at 20:15, tim lindner wrote:

> >>>

> >>>To: coco at maltedmedia.com (CoCo Mailing List)

> >>>From: tlindner at ix.netcom.com (tim lindner)

> >>>Date sent: Mon, 1 Aug 2005 20:15:58 -0700

> >>>Organization: Computers Suck, Inc.

> >>>Subject: [Coco] 6309 Division instructions

> >>>Send reply to: CoCoList for Color Computer Enthusiasts

> >>><coco at maltedmedia.com>

> >>> <mailto:coco-

> >>>request at maltedmedia.com?subject=unsubscribe>

> >>> <mailto:coco-

> >>>request at maltedmedia.com?subject=subscribe>

> >>>

> >>>>I was testing the division instructions against my 6309 core (in

> >>>>MESS) and found something unusual.

> >>>>

> >>>>My Burke & Burke 6309 documents say that result of DIVD is a

> >>>>signed 8-bit value in register B and an unsigned remainder in

> >>>>register A.

> >>>>

> >>>>Further more it says that if the quotient overflows, the value of

> >>>>A and B will be unchanged and the V condition code will be set.

> >>>>

> >>>>But this is not exactly the behiavior I am seeing on real

> >>>>hardware.

> >>>>

> >>>>What I am seeing is a sort of two stage overflow. If the quotient

> >>>>doesn't fit in an signed 8 bit container but would fit in a

> >>>>unsigned 8 bit container, then the correct absolute value is

> >>>>wirrten to B and the V condition code is set.

> >>>>

> >>>>If the value overflows an unsgined container, the registers A and

> >>>>B set to the absolute value the the orginal numerator and the V

> >>>>condition code is set.

> >>>>

> >>>>I have not seen this behiavor described anywhere and I would be

> >>>>interested in other peoples thoughts on it.

> >>>>

> >>>>--

> >>>>tim lindner

> >>>>tlindner at ix.netcom.com Bright

> >>>>

> >>>>--

> >>>>Coco mailing list

> >>>>Coco at maltedmedia.com

> >>>>http://five.pairlist.net/mailman/listinfo/coco

> >>>

> >>>

> >>>

> >>>

> >>--

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> >

> >

>

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