[Coco] [Color Computer] Re: VHDL 6809

[j_e_daggett]

--- In ColorComputer at yahoogroups.com, "John Kent" <John0457 at h...>
wrote:
> 

On the COCOs the MC6847 accesses video ram through the MC6883 SAM chip
on the second half of the E_clk. The front of first ahlf is the MPU
cycle. Therefore it does a cycle share. CPU cycle starts with the
falling edge of the E-clock. The rising edge is the VDU time. 

John due to the internal two phase clock of the 6809, a 12.5 Mhz
single phase clock VHDL model unless it takes advantage of the rising
and falling edge will only perfom at half that of what your claiming.
Address Output of the 6809 is actually latched out on the falling edge
of the Q-Clock. During the write cycle the data out is latched to the
databuss on the rising edge of the Q-Clock. The internal logic of the
processor allows some of the internal movements on the internal buss
to be synced with the Q-Clock. 

By doing this two pahse clock system the interanl workings are running
effectively at twice the E-Clock cycle. There are four states for
every E-Clock cycle to power the internal state machine. If you XOR
the E adn Q clocks you generate a 4X clcok since the two clocks are in
quadrature phase.


james



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