[Coco] assembly questions?

[jdaggett at gate.net]

Mark

Well from a hobbyists point of view, after 200K gates the only 
package that the bigger Sparrtan II's come in are BGA packages. 
That size and that fine a pitch BGA is not exactly hobbyist manual 
soldering ability unless one has a great deal of experience in 
soldering BGA packages to PCBs. 


If you are doing a commerical board where some sourcing company 
like FLextronics, Jabil or some overseas house is doing the boards 
and assembly, then it is no problem. 

I like the Xilinx web pack tools. I have not played much with the 
Altera tools. Maybe later this year. 

If one were to do a FPGA version of the 6809 or the 6309, either 
those two would be good starts. For Xilinx though, the Spartan IIE or 
the Spartan 3 would be better. The Virtex line is in my opinion to 
expensive. 

james

On 23 Jul 2004 at 14:51, Mark Marlette wrote:

Date sent:      	Fri, 23 Jul 2004 14:51:07 -0500
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From:           	Mark Marlette <mmarlett at isd.net>
Subject:        	Re: [Coco] assembly questions?
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> At 03:46 PM 7/23/2004 -0400, you wrote:

> 

> James,

> 

> Why is the Xilinx Spartan II a major problem?

> 

> Mark

> Cloud-9

> 

> 

> >Kevin

> >

> >I have investigated two open cores for the 6809 and the one major

> >problem is that they both require a 200K gate Xilinx Spartan II

> >series FPGA.

> >

> >I have started investigating this and have started some preliminary

> >work. There are at least two commercially available cores that can go

> >to either FPGA or directly to ASIC. Considering that the original

> >part was done on a 4 inch wafer and with greater than 1 micron

> >technology, this is by far inferior to modern wafer processign. Today

> >if the 6809 were to be done it would definitely be at least .25

> >micron CMOS at 3.3 VDC or lower. On today's wafer processing, the

> >speeds could easily reach 16 if not 25 MHz buss.

> >

> >james

> >

> >

> >On 23 Jul 2004 at 11:38, Kevin Diggs wrote:

> >

> >Date sent:              Fri, 23 Jul 2004 11:38:18 -0700

> >From:                   Kevin Diggs <kevdig at hypersurf.com>

> >To:                     CoCoList for Color Computer Enthusiasts

> ><coco at maltedmedia.com>

> >Subject:                Re: [Coco] assembly questions?

> >Send reply to:          CoCoList for Color Computer Enthusiasts

> ><coco at maltedmedia.com>

> >         <mailto:coco-

> >request at maltedmedia.com?subject=unsubscribe>

> >         <mailto:coco-

> >request at maltedmedia.com?subject=subscribe>

> >

> > > Hi,

> > >

> > >  The speed of these probably isn't that crucial since there are

> > > so few registers to transfer between (amongst?). If I ever find a

> > > job I think I am gonna start with that 6809 VHDL core someone did

> > > and create the 6909.  One thing I think I'll include is a set of

> > > shadow registers and some special FAST tfr and exchange

> > > instructions to get at them. Kind of like a high speed register

> > > cache. Probably also need a context save instruction. And maybe

> > > some burst bus modes for some caches. And an instruction cache.

> > > And a stack cache (to speed up stack operations). And a 16-bit

> > > internal bus. ...

> > >

> > >  I am working on an assembly port of the old X maze program. The

> > > lack of registers has been ... constantly annoying.

> > >

> > >      kevin

> > > KnudsenMJ at aol.com wrote:

> > > >

> > > > Thanks -- I myself have always wondered why TFR and EXG were so

> > > > slow! Part of the problem seem s to be always treating them as

> > > > 16-bit operations, so TFR A,B takes as long as TFR X,Y.

> > > >

> > > > And the other is using that internal temp reg, which turns out

> > > > not to be needed -- see below.

> > > >

> > > > In a message dated 7/23/04 7:53:52 AM Eastern Daylight Time,

> > > > jdaggett at gate.net writes:

> > > >

> > > > > with the TFR instrtruction the third and fourth cycle write R1

> > > > > to a temp register internally. On cycle 5 and 6 the temp

> > > > > register is written to R2.

> > > >

> > > > This sounds like an explanation I heard years ago, but below we

> > > > see the temp wasn't needed. . .

> > > >

> > > > >  With the EXG instruction the third and fourth cycle writes R1

> > > > >  to the temp

> > > > > register.

> > > > >  On the fifth and six instruction the contents of R2 is

> > > > >  written to R1. On

> > > > the

> > > > > seventh  and eighth cycles the temp register is sritten to R2.

> > > >

> > > > Since R2 was written directly to R1, the TFR instruction could

> > > > have bypassed the intermediate register too.  But I guess this

> > > > implementation simplified the control sequencing.  Remember, the

> > > > 6809 was, and remains, the most sophisticated 8/16-bit micro

> > > > ever made -- or darn close to it.

> > > >

> > > > Thanks again for the details.  BTW, does the 6309 cut out any of

> > > > these intermediate steps?  Maybe use a 16-bit internal bus?!?

> > > > --Mike K.

> > > >

> > > > --

> > > > Coco mailing list

> > > > Coco at maltedmedia.com

> > > > http://five.pairlist.net/mailman/listinfo/coco

> > >

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> >

> >

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