[Coco] Interrupt Confusion

[Roger Taylor]

At 07:04 PM 1/11/2004 -0600, you wrote:
>I'm having having a problem with two games in Mocha that appear to be 
>interrupt related - just when I thought I had all that ironed out!
>
>Here's my understanding of how things should work with regard to the 60ms 
>IRQ. Please let me know if I'm wrong.
>
>bit 0 of 0xff03 must be set to 1 to enable the interrupt
>bit 4 of the CC (IRQ Interrupt mask) must be set to zero for the cpu to 
>process the interrupt.


The F(IRQ) signals in the CoCo 1/2/3 can be confusing unless you need to 
view each chip as a routing device and know that routing can be enabled or 
disabled for any given interrupt signal.  The CPU is always the end chip 
because it is there that an automatic service address will be called 
immediately when an IRQ or FIRQ occurs.  That's the whole idea, to respond 
at any given time, without the foreground code expecting it.

The PIAs can be set to route or not route interrupt signals FROM hardware 
devices TO the CPU.  You can still manually check bit 7 of 65281, 65283, 
65313, 65315 to see if certain interrupts are occurring.

There might be cases where PIA programming can conflict with GIME 
programming when you're dealing with interrupt handling.  I always disable 
the PIA interrupt outputs to the CPU and let the GIME do everything, since 
the same things can be done by the GIME, and more.  I always thought that 
if you told a PIA to send an interrupt to the CPU whenever the 60hz refresh 
signal occurs, but then you also told the GIME to generate the same 
interrupt, that the CPU might be receiving TWO 60hz interrupts from two 
different chips.  I could be wrong about this, but for some reason over the 
years I ended up being safe and turning off interrupts from the PIAs 
whenever possible.


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Roger Taylor