[Coco] Q: Field Sync Interrupt

[jdaggett at gate.net]

Torsten

Did yo umeand $FF03 instead of $FF02? At $FF02 you are writing to the port 
register. Depending on the state of the Data direction register bit 7 will be either an 
input or output. IF it is an input then a write does nothing. 
 
The PIA registers are this. 

$FF00   Data Direction/Port register Port A
$FF01   Control Register A (CRA)
$FF02   Data Direction/Port Register Port B
$FF03   Control Register B (CRB)

By setting bit 0 of the correspnding control registers (CRA,CRB) you enable the 
corresponding IRQ output. Otherwise clearing bit 0 of the control register makes the 
CA1 and/or CB1 pin a general purpose input. Its state is read from bit 7 of the  
control register. Once this bit is read it is cleared. It is a read only bit. Writing a 1 to 
bit 7 of $FF01 or $FF03, should do nothing.   

An advantage of this way is if you are in a polling system where Interrputs are not 
generated but the software polls its outputs to see who needs serviceing. ALso the 
PIA chip can do as the COCO 3 coes and a wired ored fashion the IRQA and IRQB 
outputs. Thus the software then reads bit 7 of each control register to determine 
who genereated the IRQ. Then you place a software priority if both flags are set 
then either port A or port B can be made higher priority. 

Selction of whether Data Direction register or the Port is addressed at $FF00 and /or 
$FF02 is done by bit 2 of the respective control register. Setting bit 7 of $FF00 or 
$FF00 when configured as an input should result in a bit that will be lost in space. 

james



On 11 Jan 2004 at 15:12, Torsten Dittel wrote:

To:             	coco at maltedmedia.com
From:           	Torsten Dittel <Torsten at Dittel.info>
Date sent:      	Sun, 11 Jan 2004 15:12:32 +0100
Subject:        	[Coco] Q: Field Sync Interrupt
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> Hi,
> something on-topic ;-):
> 
> What happens exactly, if you write to Bit 7 of $FF02? I know this Bit
> is the Field Sync Interrupt Flag which (if interrupt enabled in the CC
> and in Bit 0 of $FF03) is set when an interrupt occurs each 16.67ms
> and has to be cleared by reading from address $FF02 within the
> Interrupt Service Routine to allow further IRQs.
> 
> Thanks and regards,
> Torsten
> 
> 
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