[Coco] CoCo RGB video timing and levels

[Theodore Evans (Alex)]

On Aug 24, 2004, at 5:51 PM, jdaggett at gate.net wrote:

> even still, I believe that 14.318 MHz is awfull high for a pixel clock 
> for 640 pixel
> display. A value more like 12.56 MHz would be more reasonable. If the 
> service
> manual is correct with 280 nS read from ram in the VDU cycle, even a 
> 14.28 Mhz
> pixel clock is to fast. The 8th bit is shifted out before the next 
> byte is read. It would
> seem that the pixel clock is a bit slower but I am uncertain as how 
> the designer of th
> chip derived the clock frequency without a fractinal-n divider.

It may seem high, but the CoCo isn't the only machine to use this kind 
of figure.  NTSC Amigas use approximately the same figures, 35 ns for 
super-high resolution (1280xX) 70 ns for high resolution (640xX) and 
and 140 ns for low resolution (320xX).  As far as shifting out the last 
bit you should note two things, the data bus for the GIME is 16-bits 
wide, not 8-bits, and the designers probably have the GIME buffer a 
word, so the read out is not a problem.

-- 
Theodore (Alex) Evans | 2B v ~2B = ?