[Coco] CoCo RGB video timing and levels

[jdaggett at gate.net]

Alex

The GIME chip uses what they call Interleaved DMA and what some call cycle 
sharing. The VDU reads video data from ram when the E Clock is low and when the 
E clock is high the CPU will read and write to the ram. The address buss (Z-Buss) is 
muxed between video and CPU addresses with the polarity of the E clock. 

70nS is a bit to fast for 150nS fast page mode dram. That is what the 256Kx1 drams 
are, fast page drams. 150nS is what comes standard with the 512K memboard as 
well as the stock 128K versions if I remember correctly. 

Looking at the Service manual, it looks as the if the GIME chip is running a pixel 
clock of 3.579 MHz or 280nS. In 640x200 two color mode, one read covers eight 
pixels and the VDU has to read every 8th pixel or a total of 80 reads. In 640x200 4 
color mode the VDU has to read every 4th pixel and makes a total of 160 reads. 
Plenty of time even at a buss rate of 1.78 MHz. 

james   

On 23 Aug 2004 at 20:56, Alex wrote:

From:           	Theodore (Alex) Evans <alxevans at concentric.net>
Subject:        	Re: [Coco] CoCo RGB video timing and levels
Date sent:      	Mon, 23 Aug 2004 20:56:05 -0700
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> 
>  From memory, the CoCo uses a 70ns (or 14.28MHz) pixel clock when
>  using 
> a 640x200 resolution.  As far as memory bandwidth is concerned.  The
> GIME needs to read from memory once for every 8 pixels (2 bits per
> pixel, 16 bits per read) which works out to one read for every cycle
> at 1.78 MHz.
> 
> -- 
> Theodore (Alex) Evans | 2B v ~2B = ?
> 
> 
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