[Coco] deuce memory bandwidth?

[Paul T. Barton]

James,

--- jdaggett at gate.net wrote:

> Kevin 
> 
> one other note. 
> 
> The 6809/6309 operate under a two phase clock
> system. The two 
> clocks are in quadrature and the Q clock leads
> the E clock by 90 
> degress.  All machine cycles are referenced to
> the falling edge of the E clock. 
> 
> The CPU latches data out on databuss on the
> rising edge of the E 
> clock and latches data into the core from the
> data buss on the 
> falling edge of the E clock. Data  being read
> by the CPU must be 
> stable by the falling edge of the Eclock and
> should  have a hold 
> time of about 5% of the machine cycle after the
> fall of the Eclock. 
> One more item, the address bus is valid on the
> falling edge of the Q clock.

How about rising?
I read that addresses are valid
on rising edge of Q.


> By using a two phase clock the 6809 can move
> stuff around withing 
> the processor four times faster than a CISC
> processor usign a 
> single pahse clock. If you XOR the two phase
> clocks, you get an 
> equivalent 4 times frequency clock. 
> 
> james
--snipped--



		
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