[Coco] GIME Chip Registers and the ultimate repack

[jdaggett at gate.net]

Robert

I was thinking of integrating the 6821's into the chip if room was 
there. That would require the IRQ's to come through the registers or 
external pins. Either way that is doable.

Thanks for the input.

james


On 3 Aug 2004 at 21:54, Robert Gault wrote:

Date sent:      	Tue, 03 Aug 2004 21:54:37 -0400
From:           	Robert Gault <robert.gault at worldnet.att.net>
To:             	CoCoList for Color Computer Enthusiasts 
<coco at maltedmedia.com>
Subject:        	Re: [Coco] GIME Chip Registers and the 
ultimate repack
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> jdaggett at gate.net wrote:
> > hello
> > 
> > After seeing a few repacks of COCO3's I started mulling over an idea
> > of repacking and modernizing the coco a bit. I have started coding
> > some VHDL code to do the GIME chip in an FPGA. So far the MMU is
> > coded and syntesized and directly addresses 2  megs of ram. The
> > datram is a 16x8 and not the 16x6 currently used. Looks like the MMU
> > can run at 40 MHz with no problem.  The plan is to use fast SRAM for
> > my repack. 512Kx8 20nS SRAM are relatively cheap, under $10 each.
> > 512Kx8 70nS SRAMs are under $5. 
> > 
> > After reading the Unraveled Series and studying the service manual I
> > have basically one area of concern. That is the INIT0 register
> > located at $FF90. From what I gather on cold restart or power up,
> > after coming out of reset it appears that the GIME chip is set with
> > the MMU off and in COCO 3 mode. RSBAsic initializes the INIT0
> > register and then programs the task registers at $FFA0 to $FFAF with
> > proper vlaues. 
> > 
> > What I contend to do is to come out of reset and have the INIT0
> > register default to $4E. That is:
> >   bit 7 - "0"
> >   bit 6 - "0"
> >   bit 5 - "1"
> >   bit 4 - "1"
> >   bit 3 - "1"
> >   bit 2 - "1"
> >   bit 1 - "1"
> >   bit 0 - "0"
> > 
> > I think this will still be compatible with the RS Basic rom? Anyone
> > sure of this?
> > 
> > I have to finish up coding the register stack to at least $FF97. I
> > have planned usage for $FF96 and $FF97 to drive an external clock
> > chip to generate various CPU bus speeds separate from the video
> > clock. After that it will be on to the video section.
> > 
> > Thinking of putting a RTC at $FF80 to $FF8F also.
> > 
> > Mind boggling as to what one can do with these FPGAs.
> > 
> > 
> > james
> > 
> That might not be a good idea because you will have the GIME IRQ and
> FIRQ engaged before the ROM has a chance to set any vectors. A safer
> value would be $0E. In any case, the first thing the Basic ROM will do
> is set $FF90 to %11001110 or $CE.
> 
> 
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